1. Field of the Invention
The present invention generally relates to floating point mathematical data processors and, more particularly, to arrangements for converting the format of binary numbers to an expanded, high-resolution format for mathematical processing.
2. Description of the Prior Art
Programmed digital data processors are particularly suited to the performance of extended repetitive and complex operations on data. In regard to mathematical data, once programmed, a data processor can precisely carry out complex computational algorithms for solving or approximating solutions to problems of a complexity which cannot be effectively approached in any other way. Simulations of three dimensional fluid flow systems is an example of such a complex problem.
In complex computations, a particular numerical quantity may be sequentially subjected to numerous separate computations. However, the digital nature of data processors requires that the quantity be expressed in terms of a radix which, unless the expression is of infinite length, may not allow an exact expression of the value of the quantity. Conversely, since any practical processor cannot accommodate expressions of infinite length, many quantities involved in any computation may include slight variations from true values. When such quantities are subjected to numerous sequential computations, often including other quantities having similar slight inaccuracies, the cumulative error can become significant unless compensating adjustments are made.
For this reason, it is the usual practice to periodically store numerical expressions of values used in computations expressed in a so-called single precision (32 bits: 1 sign bit, 8 exponent bits and 23 mantissa bits) or double precision (64 bits: 1 sign bit, 11 exponent bits and 52 mantissa bits) format having standardized numbers of (generally binary) digits in a mantissa and exponent but to use many more such digits in a so-called extended real (80 bits: 1 sign bit, 15 exponent bits and 64 mantissa bits) or similar format internally of the processor to carry out the computation. The increased resolution of the increased number of digits of the extended real format together with selective use of a plurality of rounding techniques to reduce the expression to single precision or double precision format is quite successful in suppressing cumulative errors to levels smaller than can be reflected in a single-precision or double-precision output or other, lesser, precision as may be specified in the computational algorithm. Of course, it should be understood that the expression of the number value could be stored in extended real or higher resolution format and an even higher resolution format used internally of the processor for computation.
When a number is retrieved from memory for use in a computation or after mathematical operations such as subtraction, multiplication or division, it is not initially known whether or not the number is in a normalized form. Further, after retrieval from storage, the mantissa of the number must also be generally expanded from the format in which it is stored to the format (e.g. extended real format) for use internally of the processor.
Expansion and normalization are generally performed by shifting while accumulating a number for subtraction from the exponent to compensate for the shifting (and which will be retained as a shift value for restoring or reconverting the number when the result is to be stored). For expansion of a normalized mantissa, the number of bits of shifting which is required is generally known from the initial and target number formats. These formats are fairly well standardized at the present time and only a few shift numbers, readily stored in and retrieved from memory, are generally required. Normalization is generally performed separately by detecting the number of leading zeros and shifting by that number of bits. "Handling Leading Zeros in a Data Processing Unit" by Gooding et al., IBM Tech. Discl. Bull., Vol. 17, No. 10, pp. 2844-2845, March, 1975, is exemplary of such arrangements.
Whether or not normalization is necessary will be evident from the logic state of the most significant bit of the number. As a consequence, such shifters have generally been organized to initially shift by small increment (e.g. one bit) and then larger increments (e.g. 2, 4, 8, 16 and 32 bits, in order, the 32 bit shift being generally implemented as two sixteen bit shift operations) so that the most significant bit is initially made available to determine if normalization is necessary. If normalization is not necessary, shifting by a known number of bits remains necessary for number format conversion.
If normalization is thus found to be necessary, shifting for normalization is placed in a processing pipeline subsequent to shifting for conversion from a storage format to an internal processing format. This sequence of separate operations is sufficiently extended that it cannot be done in a single processing cycle and is the longest path in a so-called load special function unit of the processor. Therefore, a processing pipeline is required to accommodate the cycle time objective of modern mathematical processors.
Thus, it can be seen that the sequential operations as well as the pipeline contribute to the time required for computations and memory fetches and storage operations. It may be especially appreciated that while the counting of leading zeros and shifting operations can be carried out very rapidly, the total time required for a complex computation can become extended due to the number of times normalization and format conversion must be performed (e.g. for each computation or small series of computations sufficient to prevent error accumulation) when the counting of leading zeros and shifting must be performed separately and sequentially, even when pipelined.